Build the FPGA Bitstream

Normal Mode :

To build FPGA bitstream, you can simply add the following command line option to ocaccel_workflow.py:

./ocaccel_workflow.py --make_image

With --make_image, ocaccel_workflow.py will start building image after finishing simulation.

If you just want to start building the bitstream without running simulation, please run with the following commands:

./ocaccel_workflow.py --no_make_model --no_run_sim --make_image

Partial Reconfiguration (PR) case (check the PR section​ for more details):

• if you just want to start building a reference image (including a reference base as well as a default action), please run with the following commands:

./ocaccel_workflow.py --no_run_sim --image_mode=cloud_base

• if you just want to start building an action image, please run with the following commands:

./ocaccel_workflow.py --no_run_sim --image_mode=cloud_action

Check the Result of FPGA Bitstream

Basic Result

The basic concepts and flows of building FPGA bitstream, including synthesis, place, route and optimization, can be found in Xilinx official documentation ug904.

After finishing the whole bitstream building process, ocaccel_workflow.py will notify the user if vivado is managed to generate bitstream by giving a FAILED or PASSED message. More detailed messaging can be found in ocaccel_workflow.make_image.log in the root directory.

If the bitstream is generated, they can be found in the following directory:

<ocaccel root>/hardware/build/Images

Just take the *.bin or *.bit file in that directory to program the FPGA card according to your own system requirements.

Further Debugging Materials if Bitstream Generation Failed

If the bitstream is not generated, possibly due to failure of closing timing and/or over-utilization, there are following files for user to further root cause.

The reports, including timing report and utilization report:

<ocaccel root>/hardware/build/Reports

Reports in this directory is generated by Vivado for different stages/phases during the bitstream generation. Please refer to Xilinx Vivado documentation for further explanation.

The checkpoints, which allows user to check the status after each stages/phases in Vivado GUI:

<ocaccel root>/hardware/build/Checkpoints

Specify Bitstream Generation Strategy

Vivado has a rich set of strategies/directives for user to choose during bitstream generation (implementation), which has been explained in ug904.

By default, ocaccel_workflow.py uses "Explore" as the strategy which means for all the stages/phases, the directive is "Explore". You can change this setting by putting a tcl file with strategy settings in the following directory:

<oaccel root>/actions/<your action>/hw/tcl/

For example, a file named strategy.tcl can be put in above directory, with the following contents:

set_property strategy  "Flow_PerfOptimized_high" [get_runs synth_1];
set_property strategy "Performance_NetDelay_high" [get_runs impl_1];

These settings tell Vivado to use Flow_PerfOptimized_high during synthesis, and Performance_NetDelay_high during implementation.